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CXP82712/82716
CMOS 8-bit Single Chip Microcomputer
Description The CXP82712/82716 microcomputer is composed of a 8-bit CPU, ROM, RAM, and I/O ports. These chips feature many other high-performance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time base timer, fluorescent display controller/driver, remote control receiver, PWM output circuit and 32kHz timer/counter. This device also includes sleep/stop functions which can be used to achieve low power consumption. 64 pin SDIP (Plastic)
Structure Silicon gate CMOS IC
Features * Instruction set which supports a wide array of data types -- 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean bit operations. * Minimum instruction cycle 400ns for 10MHz, 122s for 32kHz operation * On-chip ROM 12K bytes (CXP82712) 16K bytes (CXP82716) * On-chip RAM 448 bytes (Including fluorescent display data area) * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation system (conversion rate 32s/10MHz) -- Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer), 1 circuit 2-channel -- Timers 8-bit timer 8-bit timer/counter 19-bit time base timer 32kHz timer/counter -- Fluorescent display controller/driver 24 high voltage tolerance output ports Maximum of 144 segments display available 1 to 16 digits dynamic display Dimmer function High voltage tolerance output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum of 8 x 8 key matrix available) -- Remote control receiver circuit On-chip 6-stage FIFO 8-bit pulse measurement counter -- PWM output 8-bit, 1-channel * Interruption 13 factors, 13 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 64-pin plastic SDIP * Piggyback/evaluator CXP82700 64-pin ceramic SDIP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93Y23A79-PS
Block Diagram
PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE3/NMI
8
A/D CONVERTER SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL
PH1/TEX PH0/TX EXTAL XTAL RST VDD Vss
8
8
PORT A
PA0/AN0 to PA7/AN7
8
PA0 to PA7
T0 to T7 T8/S28 to T15/S21 S13 to S20 VFDP RAM 80 BYTES FIFO ROM 12K/16K BYTES
INTERRUPT CONTROLLER
RAM 448 BYTES
PORT C
PE4/RMC
REMOCON
PORT B
8
FDP CONTROLLER/ DRIVER
8
PB0 to PB7
8
PC0 to PC7
PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 PB0/CS1 PB6/SI1 PB7/SO1 PB5/SCK1 FIFO 2 PRESCALER/ TIME BASE TIMER
SERIAL INTERFACE UNIT
PE5/PWM
8 BIT PWM
PE0/EC 2
8 BIT TIMER/COUNTER 0
PORT F
32kHz TIMER/COUNTER
PORT E
PE6/ADJ
PORT H
-2-
6 2
PE0 to PE4 PE5 to PE6
3
PF5 to PF7
PE6/TO
8 BIT TIMER 1
2
PH0 to PH1
CXP82712/82716
CXP82712/82716
Pin Assignment (Top View)
PH0/TX PH1/TEX NC PE6/ADJ/TO PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD PE5/PWM PE4/RMC PE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/EC/INT0 VFDP T0 T1 T2 T3 T4 T5 T6 T7 T8/S28 T9/S27 T10/S26 T11/S25 T12/S24 T13/S23 T14/S22 T15/S21 S20 S19 S18 S17 S16 PF7/S15 PF6/S14 PF5/S13
Note) 1. NC (Pin 3) is always connected to VDD. 2. PH0/TX (Pin 1) is input port during port selection; oscillation output during oscillation selection -3-
CXP82712/82716
Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/Analog Input
Analog inputs to A/D converter. (8 pins)
PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port C) 8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
PC0/KR0 to PC7/KR7
I/O/Input
Key return input for FDP segment signal which performs key scanning.
PE0/INT0/ EC0 PE1/INT1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5/PWM PE6/ADJ/TO
Input/Input/ Input Input/Input Input/Input Input/Input/ Input Input/Input Output/Output Output (Port E) Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins)
External interrupt requests. (4 pins)
External event input to timer/counter. (1 pin)
Non-maskable interruption request input. Input for remote control receiver circuit. 8-bit PWM output. Output for timer/counter rectangular waveform and 32kHz oscillation frequency division.
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CXP82712/82716
Symbol PF5/S13 to PF7/S15 S16 to S20 T8/S28 to T15/S21 T0 to T7 VFDP EXTAL XTAL PH1/TEX PH0/TX RST NC VDD Vss Input
I/O Output/Output Output Output/Output Output (Port F) 3-bit output port. (3 pins)
Functions Segment signal output for FDP.
Segment signal output for FDP. Dual purpose output for FDP timing and segment signals. Timing signal output for FDP. Provides voltage for FDP when on-chip resistor is selected under mask option. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. (Port H) 2-bit input port. (2 pins) Crystal connectors for 32kHz timer/counter clock oscillation circuit. Connect a 32kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and leave TX open.
Output Input/Input Input/Output Input
System reset pin of active "L" level. RST is input pin. NC. Under normal operating conditions, connect to VDD. Vcc supply. GND
-5-
CXP82712/82716
I/O Circuit Format for Pins Pin Port A
Pull-up resistor "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset A/D converter
Input multiplexer Pull-up transistors approx. 100k
8 pins Port B
Pull-up resistor "0" when reset
PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B data
Port B direction "0" when reset Schmitt input RD (Port B)
IP
Hi-Z
4 pins Port B
Pull-up resistor "0" when reset SCK OUT Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset
CS0 CS1 SI0 SI1
Pull-up transistors approx. 100k
PB2/SCK0 PB5/SCK1
IP
Hi-Z
Data bus RD (Port B)
Schmitt input
2 pins
SCK in
Pull-up transistors approx. 100k
-6-
CXP82712/82716
Pin Port B
Pull-up resistor "0" when reset SO Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset
Circuit format
When reset
PB4/SO0 PB7/SO1
IP
Hi-Z
Data bus RD (Port B)
2 pins Port C
Pull-up resistor "0" when reset Port C data
Pull-up transistors approx. 100k
2
PC0/KR0 to PC7/KR7
Port C direction "0" when reset Data bus RD (Port C) Key input signal
1
IP
Hi-Z
8 pins Port E PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC 5 pins
1 Large current drive of 12mA possible 2 Pull-up transistors approx. 100k
Schmitt input IP
EC/INT0 INT1 INT2 INT3/NMI RMC Data bus RD (Port E)
Hi-Z
-7-
CXP82712/82716
Pin Port E
Circuit format
When reset
PWM Port E output selection
PE5/PWM
"0" when reset Port E data "1" when reset Output enable
High level
Data bus RD (Port E)
1 pin Port H
Output enable TO ADJ16K ADJ2K Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data ADJ signals are frequency division outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output.
MPX
PE6/TO/ADJ
(
High level High level with 150k resistor when reset
)
1 pin
"1" when reset Data bus RD (Port E)
Port F
High voltage tolerance transistor Segment output data
PF5/S13 to PF7/S15
Output selection control signal ("0" when reset) Port F data Pull-down resistor Data bus RD (Port F) VFDP
OP Mask option
(
Hi-Z or Low level When PD resistor is connected
)
3 pins
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CXP82712/82716
Pin
Circuit format
High voltage tolerance transistor
When reset
S16 to S20 T15/S21 to T8/S28 T0 to T7
Segment output data Output selection control signal ("0" when reset)
OP Mask option
Pull-down resistor
(
VFDP
Hi-Z or Low level When PD resistor is connected
)
21 pins
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit construction for oscillation. * During stop feedback resistor is disconnected. At this time XTAL pin outputs "H" level.
Oscillation
2 pins
XTAL
32kHz oscillation circuit control "1" when reset Data bus RD
PH1/TEX PH0/TX
PH2/TEX IP IP
Data bus RD Clock input
Oscillation halted port input
2 pins
PH0/TX
Pull-up resistor
RST
OP Mask option
Low level
Schmitt input
1 pin
IP
-9-
CXP82712/82716
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Display output voltage Symbol VDD VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL IOLC Low level total output current IOL Operating temperature Storage temperature Allowable power dissipation Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 VDD - 40 to VDD + 0.3 -5 -15 -35 -40 -100 15 20 100 -20 to +75 -55 to +150 1000 Unit V V V V mA mA mA mA mA mA mA mA C C mW Remarks
(Vss = 0V)
As P channel transistor is open drain, VDD voltage is determined as standard. Other than display output pins2: per pin Display output S13 to S20: per pin Display output T0 to T7, T8/S28 to T15/S21: per pin Total of pins other than display output pins Total of display output pins Port 1 pin Large current port3 : per pin Entire pin total
1 VIN and VOUT must not exceed VDD + 0.3V. 2 Specifies output current of general-purpose I/O ports. 3 The large current drive transistor is an N-ch transistor of Port C (PC). Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected.
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CXP82712/82716
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD Unit V V V V V V V V V V C Remarks
(Vss = 0V)
High speed mode (1/2, 1/4 dividing clock) guaranteed operation range Low speed mode (1/16 dividing clock) guaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold operation range during stop 1 Hysteresis input2 EXTAL pin3 1 Hysteresis input2 EXTAL pin3
Supply voltage
VDD
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
1 All regular input port (PA, PB4, PB7, PC, PH). 2 For pins RST, CS0, CS1, SCK0, SI0, SI1, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC. 3 Specifies only for external clock input.
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CXP82712/82716
Electrical Characteristics DC Characteristics Item Symbol Pin PA, PB, PC, PE5, PE6 PC IIHE IILE IIHT Input current IILT IILR IIH IIL Display IOH output current Open drain output leak current (P-CH Tr off state) Pull-down resistor3 TEX RST1 PA to PC2 S13 to S20 S21/T15 to S28/T8 T0 to T7 S13 to S20 S21/T15 to S28/T8 T0 to T7 S13 to S20 S21/T15 to S28/T8 T0 to T7 PA to PC2, PE0 to PE4 RST2 VDD = 4.5V VOH = VDD - 2.5V EXTAL Condition VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V, VIL = 0.4V -8 -20 0.5 -0.5 0.1 -0.1 -1.5 3.3 50 (Ta = -20 to +75C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A A A mA mA
High level VOH output voltage Low level output voltage VOL
ILOL
VDD = 5.5V VOL = VDD - 35V VFDP = VDD - 35V
-20
A
RL
VDD = 5V VFDP = VDD - 35V
60
100
270
k
Input/Output leak current
IIZ
VDD = 5.5V VI = 0, 5.5V High-speed mode operation (1/2 frequency dividing clock)
10
A
IDD1
VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD Sleep mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, 10MHz termination of 10MHz and 32kHz crystal oscillation. - 12 -
20
40
mA
IDD2 Supply current4
35
100
A
IDDS1
1.2
8
mA
IDDS2
9
30
A
IDDS3
10
A
CXP82712/82716
Item
Symbol
Pin Pins other than S13 to S28, T0 to T7, PE5, PE6, VDD, Vss, VFDP
Codition
Min.
Typ.
Max.
Unit
Input capacitance
CIN
1MHz clock 0V for pins other than the measured pins
10
20
pF
1 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 2 Pins PA to PC specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 3 Applies when the on-chip pull-down resistor is selected under the mask option. 4 All output pins are left open.
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CXP82712/82716
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 50
32.768
kHz
tTL, tTH tTR, tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 2. Clock applied conditions
TEX EC
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
Fig. 3. Event count clock timing - 14 -
CXP82712/82716
(2) Serial transfer Item CS0 SCK0 (CS1 SCK1) delay time CS0 SCK0 (CS1 SCK1) float delay time CS0 SO0 (CS1 SO1) delay time CS0 SO0 (CS1 SO1) float delay time CS0 (CS1) high level width SCK0 (SCK1) cycle time SCK0 (SCK1) high and low level widths SI0 (SI1) input seup time (for SCK0 (SCK1 ) ) SI0 (SI1) input hold time (for SCK0 (SCK1 ) ) SCK0 SO0 (SCK1 SO1) delay time Note 1) Symbol Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Min. Max. Unit
tDCSK
SCK0 Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) (SCK1) (SCK0 (SCK1) = output mode) SO0 (SO1) (SO1) (CS1) Chip select transfer mode Chip select transfer mode Chip select transfer mode
1.5tsys + 200 ns 1.5tsys + 200 ns 1.5tsys + 200 ns 1.5tsys + 200 ns
tDCSKF SCK0 Chip select transfer mode tDCSO
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 200
2tsys + 200 16000/fc
ns ns ns ns ns ns ns ns ns
SCK0 Input mode (SCK1) Output mode SCK0 Input mode (SCK1) Output mode SI0 (SI1) SI0 (SI1) SO0 (SO1) SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode
tsys+100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200 ns
100 ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
- 15 -
CXP82712/82716
tWHCS
CS0 (CS1)
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 (SCK1) 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 (SI1) Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 (SO1) Output data 0.2VDD
Fig. 4. Serial transfer timing
- 16 -
CXP82712/82716
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = AVSS = 0V -10 4930 160/fADC3 12/fADC3 AN0 to AN7 0 VDD 70 5050 Symbol Pin Condition Min. Typ. Max. 8 3 150 5120 Unit Bits LSB mV mV s s V
tCONV tSAMP
Analog input voltage VIAN
FFH FEH
Linearity error 01H 00H VZT Analog input VFT
1 VZT : Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT : Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to the Bit6 (CKS) of A/D control register (address: 00F9H) and the Bit7 (PCK1) and Bit6 (PCK0) of clock control register (address: 00FEH)
Digital conversion value
CSK PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
Fig. 5. Definition of A/D converter terms
- 17 -
CXP82712/82716
(4) Interruption, reset input Item
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit
External interruption high and low level widths
tIH tIL tRSL
1
s
Reset input low level width
32/fc
s
tIH
tIL
0.8VDD INT0 INT1 INT2 INT3 NMI (NMI is specified only for the falling edge) 0.2VDD tIL tIH
Fig 6. Interruption input timing
tRSL
RST 0.2VDD
Fig. 7. RST input timing
- 18 -
CXP82712/82716
Appendix
(i) Main clock (ii) Main clock (iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2 C1 C2
C1
C2
Fig. 8. Recommended oscillation circuit
Manufacturer
Model CSA4.19MG CSA8.00MTZ
fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19
C1 (pF)
C2 (pF)
Rd ()
Circuit example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW
RIVER ELETEC HC-49/U03 CORPORATION .
12
12
0 (i)
27 20 50
27 20 22
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
0
P3
32.768kHz
1M
(iii)
Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2).
Mask Option Table Item Reset pin pull-up resistor High tension proof pull-down resistor Non-existent Non-existent Content Existent Existent (selected every pin)
- 19 -
CXP82712/82716
Characteristics Curves
IDD vs. VDD
(fc = 10MHz, Ta = 25C, Typical) 20.0 10.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode
IDD - Supply current [mA]
5.0
IDD - Supply current [mA]
15 1/4 dividing mode
1.0 0.5
Sleep mode
1/16 dividing mode 10
0.1 (100A) 0.05 (50A)
32kHz mode (instruction)
32kHz Sleep mode
5 Sleep mode
0.01 (10A) 3 6 2 4 5 VDD - Supply voltage [V] 7 0 5 10 fc - System clock [MHz] 15
- 20 -
CXP82712/82716
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 1.778 0.5 0.1 0.9 0.15
1
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g
- 21 -
3.0 MIN
0.5 MIN + 0.4 4.75 - 0.1

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